System Interrupts

System interrupt documentation for the Atari 8-bit computers.

Overview

There are four types of interrupts which can occur with the 6502 microprocessor:

Chip reset
IRQ (interrupt request, maskable)
NMI (non-maskable interrupt)
Software interrupt (BRK instruction)

Chip Reset

On the 400/800 the chip reset occurs only upon power-up and causes the computer to do a cold start. On later models, pressing [SYSTEM RESET] will cause a chip reset but the computer then does a warm start. On the 400/800, the [SYSTEM RESET] key generates a NMI interrupt.

Cold Start

This is a synopsis of the cold start routine:

The warm start flag [$0008] is set to 0 (false)
If a cartridge slot contains a diagnostic cartridge, control is handed to the cartridge
The end of RAM is determined by trying to complement the first byte of each 4K block of memory
Hardware registers at $D000 - $D4FF (except $D100 - $D1FF) are cleared
RAM is cleared from $0008 to the top of RAM
The user program jump vector, DOSVEC [$000A] is set to point to the black board mode (Atari logo display mode in XL/XE models)
The screen margins are set to 2 and 39
Interrupt vectors are initialized
Bottom of free RAM pointer, MEMLO [$02E7], is set to point to $0700
Resident CIO handlers are initialized
If the [START] key is pressed the cassette boot request flag, CKEY [$004A], is set
The CIO device table is initialized
If a cartridge is present it is initialized
Channel 0 is opened to the screen editor. The top-of-free-RAM pointer, MEMTOP [$02E5], is set to point below the screen region
If the cassette boot flag is set the cassette is booted
If there is no cartridge present or a cartridge doesn't prevent it, the disk is booted
The cold start flag is reset
If there is a cartridge present, the computer jumps to the cartridge's run vector
If there is no cartridge present the computer jumps through the vector DOSVEC [$000A (10)]

Warm Start

The warm start flag is set to $7F (true)
Cold start steps 2 - 4 are executed
RAM is cleared from $0010 - $007F and $0200 - $03FF
Cold start steps 7 - 14 are executed
If cassette booted software is present the computer JSRs through CASINI [$0002]
If disk booted software is present the computer JSRs through DOSINI [$000C (12)]

The difference between cold start and warm start is the condition of the warm start flag, WARMST, [$0008]. If this flag is 0 a complete cold start is executed. If the flag is anything other than 0 then only the warm start part of the warm start/cold start code is executed.

Non-Maskable Interrupts (NMI)

NMI interrupts are generated by the following conditions:

Display list interrupt - Generated by the ANTIC chip
TV vertical blank interrupt - Generated by the ANTIC chip
[SYSTEM RESET] key - (400/800)

When an NMI interrupt occurs, the hardware register NMIST [$D40F] is examined to determine what type of interrupt occurred. The computer is then directed through the proper RAM vector to service the interrupt.

Display List Interrupts (DLIs)

The computer makes no use of DLIs by default. The RAM vector points to an RTI instruction.

See Display List Interrupts for complete DLI documentation.

Vertical Blank Interrupts (VBIs)

There are two stages to the VBI service routine. The second stage is only done if a critical function was not interrupted.

Stage 1 (VBI):

The real time clock, RTCLOK [$0012 - $0014], is incremented
The attract mode variables are processed
System timer 1 is decremented. If it goes to zero the computer JSRs through system time-out vector 1

Stage 2 (VBI):

The hardware registers are loaded with the data in their shadow registers
System timer 2 is decremented. If it goes to zero the computer JSRs through the system time-out vector 2
System timers 3, 4, and 5 are decremented. If a timer goes to zero the computer sets system timer flags 3, 4, and/or 5
If auto-repeat is active, the auto-repeat process is done
The keyboard debounce timer is decremented if not 0
Information at the controller port registers is read, processed and placed in the proper shadow registers

[SYSTEM RESET] Interrupt

If a [SYSTEM RESET] interrupt is generated on the 400/800 the computer jumps to the warm start routine.

Interrupt Requests (IRQ)

When an IRQ interrupt occurs the hardware register IRQST [$D20E], the PIA status registers, PACTL [$D302] and PBCTL [$D303] are examined to determine what caused the interrupt.

For each interrupt, the 6502 accumulator is pushed to the stack. The computer is then directed to the proper RAM vector to service the interrupt.

Software Interrupt (BRK)

The operating system doesn't use software interrupts. The software interrupt vector points to a PLA followed by an RTI.

Interrupt Vectors

Label	Address	Type	Function
VDSLST	$0200	NMI	DLI - Points to an RTI
VVBLKI	$0222	NMI	Stage 1 VBI
VVBLKD	$0224	NMI	Return-from-interrupt routine
CDTMA1	$0226	NMI	Time-out 1 (used by SIO)
CDTMA2	$0228	NMI	Time-out 2 (not used by OS)
VPRCED	$0202	IRQ	Not used (points to PLA,RTI)
VINTER	$0204	IRQ	Not used (PLA,RTI)
VKEYBD	$0208	IRQ	Keyboard interrupt
VSERIN	$020A	IRQ	Used by Serial I/O routine
VSEROR	$020C	IRQ	Used by SIO
VSEROC	$020E	IRQ	Used by SIO
VTIMR1	$0210	IRQ	Not used by OS (PLA,RTI)
VTIMR2	$0212	IRQ	Not used by OS (PLA,RTI)
VTIMR4	$0214	IRQ	?
VIMIRQ	$0216	IRQ	Main IRQ code
VBREAK	$0206	BRK	Unused by OS (PLA,RTI)

System Timers

The following timers are updated during vertical blank (VBI) as noted above. If a timer is decremented to 0 the computer jumps through its associated vector or sets its associated flag.

Label	Address	Flag/Vector
RTCLOK	$0012	3 byte clock ($0012 = MSB)
CDTMV1	$0218	CDTMA1 $0226 vector (SIO time-out)
CDTMV2	$021A	CDTMA2 $0228 vector
CDTMV3	$021C	CDTMF3 $022A flag
CDTMV4	$021E	CDTMF4 $022C flag
CDTMV5	$0220	CDTMF5 $022E flag

Hardware Interrupt Control

There are two registers on the ANTIC chip which control interrupts. These registers can be used to disable interrupts if necessary. There are also two associated interrupt status registers.

The IRQ enable and status registers use the same address. The result is that reading the register does not reveal the enabled interrupts but the interrupts pending. IRQ interrupt enable data should usually be written to the OS shadow first. Reading the OS shadow tells which interrupts are enabled.

Non-Maskable Interrupt Enable

NMIEN $D40E

7 6 5 4 3 2 1 0
----------------
| | | not used  |
----------------

Bit 7: 1 = DLI enabled
Bit 6: 1 = VBI enabled

Non-Maskable Interrupt Status

NMIST $D40F

7 6 5 4 3 2 1 0
----------------
| | | | not used|
----------------

Bit 7: 1 = DLI pending
Bit 6: 1 = VBI pending
Bit 5: 1 = [SYSTEM RESET] key pending

Interrupt Request Enable

IRQEN $D20E

7 6 5 4 3 2 1 0
----------------
| | | | | | | | |
----------------

Bit 7: 1 = [BREAK] key interrupt enable
Bit 6: 1 = keyboard interrupt enable
Bit 5: 1 = serial input interrupt enable
Bit 4: 1 = serial output interrupt enable
Bit 3: 1 = serial output-finished interrupt enable
Bit 2: 1 = timer 4 interrupt enable
Bit 1: 1 = timer 2 interrupt enable
Bit 0: 1 = timer 1 interrupt enable

IRQEN has a shadow register, POKMSK [$0010 (16)].

Interrupt Request Status

IRQST $D20E (read)

7 6 5 4 3 2 1 0
----------------
| | | | | | | | |
----------------

Bit 7: 1 = [BREAK] key interrupt pending
Bit 6: 1 = keyboard interrupt pending
Bit 5: 1 = serial input interrupt pending
Bit 4: 1 = serial output interrupt pending
Bit 3: 1 = serial output-finished interrupt pending
Bit 2: 1 = timer 4 interrupt pending
Bit 1: 1 = timer 2 interrupt pending
Bit 0: 1 = timer 1 interrupt pending

Wait for Horizontal Sync

Writing any number to WSYNC [$D40A (54282)] will cause the computer to stop and wait for the next TV horizontal sync.

It is wise to use DLIs one TV line before needed then writing to WSYNC. This will keep other interrupts from causing DLIs to be serviced late. This can cause a DLI to change something in the middle of a scan line.

Important Addresses

Name	Address	Description
POKMSK	$0010	IRQEN shadow
IRQEN	$D20E	Enables IRQs when written to
IRQST	$D20E	Gives IRQs waiting when read
PACTL	$D302	Peripheral A interrupt control
PBCTL	$D303	Peripheral B interrupt control
WSYNC	$D40A	Wait for horizontal sync
NMIEN	$D40E	NMI enable
NMIST	$D40F	NMI status